PCB Layout Capabilities
Kingdta's PCB layout engineers have deep expertise across all major design disciplines. For high-speed digital designs, we apply rigorous differential pair routing, length matching, and reference plane management to ensure signal integrity at frequencies up to 56 Gbps. For RF and microwave designs, we work with Rogers, PTFE and Taconic substrates, applying precise transmission line calculations and isolation techniques.
Power electronics layouts receive special attention to thermal management, current-carrying capacity, and loop inductance minimization. Every layout undergoes our internal DFM review before Gerber release, ensuring seamless handoff to our fabrication and assembly lines.
Technical Specifications
| Parameter | Capability |
|---|---|
| Max Layers | 32 layers |
| Min Trace Width | 0.075mm (3mil) |
| Min Trace Spacing | 0.075mm (3mil) |
| Min Via Drill | 0.2mm |
| Min Microvia Drill | 0.1mm (laser) |
| Controlled Impedance | ±10% tolerance |
| BGA Pitch | 0.4mm minimum |
| Max Pin Count | 100,000+ pins |
| Board Size | Up to 600 × 500mm |
| Design Tools | Altium, KiCad, Allegro, Eagle |
8-Layer PCB Layout for a Software-Defined Radio (SDR) Receiver
A Canadian RF engineering company developing a 70 MHz – 6 GHz software-defined radio receiver for spectrum monitoring — requiring an 8-layer PCB layout with controlled impedance RF traces, a dense FPGA section, and a high-speed USB 3.0 interface.
The Problem
The customer's previous layout contractor had delivered a board with 14 DRC violations and a FPGA BGA fanout that used via-in-pad without resin fill, making the design unmanufacturable at target price. The RF section had trace impedance deviations of up to ±8Ω from the 50Ω target due to inconsistent reference plane management.
Key Challenges
- 50Ω controlled impedance on RF traces from SMA connectors to ADC inputs — ±3Ω tolerance
- Xilinx Artix-7 FPGA in 484-ball BGA — fanout requiring 4 routing layers
- USB 3.0 differential pairs — 90Ω differential impedance, length-matched to ±0.1mm
- RF section isolation from digital section — split ground plane with controlled crossing points
- 8-layer stack-up with 4 signal layers and 4 plane layers
Our Solution
We redesigned the layout from scratch using Altium Designer with our in-house 8-layer stack-up verified for impedance control. The RF traces use coplanar waveguide with ground (CPWG) topology on Layer 1 with a solid ground reference on Layer 2, achieving ±2.1Ω impedance consistency. The FPGA BGA fanout uses a dog-bone via pattern on Layers 1–2 with microvias on Layers 3–4, eliminating via-in-pad. USB 3.0 differential pairs are length-matched to ±0.05mm. The RF and digital sections are separated by a moat in the ground plane with a single controlled crossing point at the ADC.
Results & Outcomes
"The layout Kingdta delivered was a completely different quality level from our previous contractor. The impedance control documentation they provided — with measured vs. simulated values for every RF trace — was exactly what we needed to validate the design before committing to production. First prototype worked first time."
RF Systems Engineer, SDR Company — Ottawa, Canada